1. Field of the Invention
The present invention relates to the generation of pulse trains by means of a microprocessor. It more specifically relates to the generation of variable width trains of variable frequency digital pulses, the respective widths of the trains and the pulses being programable by means of a CPU of a microprocessor. Such generation of pulse trains is used, for example, in infrared remote controls for monitoring infrared-emitting diodes, the sequence in which the pulse trains are generated and/or their number of pulses constituting a control code likely to be decoded by a receiver of the transmitted infrared signals.
More generally, the present invention applies to the generation of a discontinuous pulse sequence for which it is desired to program both the pulse frequency and the width of the trains or successive pulse series.
2. Discussion of the Related Art
FIG. 1 shows, partially and in the form of a block-diagram, an example of a conventional implementation of a programable pulse train generator.
Such a generator includes a CPU 1 for executing an instruction program previously stored in a memory (not shown). CPU 1 conventionally is associated with a timer 2 which can be used as a time base for exchanges between the microprocessor and an external peripheral, for example, an infrared-emitting diode (not shown).
CPU 1 is also associated with a prescaler 3, the function of which is to shape an external clock CLKE and deliver to CPU 1 and timer 2 an operating clock CLK0. Prescaler PS 3 is programmable via a first register (PS-REG) 4 to set the division rate of external clock CLKE and, thus, the operating frequency of CPU 1.
Timer 2 is programmable by CPU 1, via certain bits of register 4 and of a second register (T-REG) 5 which are programmed by CPU 1. The timing frequency is given by clock signal CLK0.
CPU 1 communicates with registers 4 and 5 via an address bus 6, a data bus 7 and a control bus (not shown). Although not shown for the sake of clarity, CPU 1 also communicates via the buses with timer 2 to ensure its control as well as with other conventional components (not shown) of the microprocessor.
Timer 2, for example, comprises a digital flip-flop counter (not shown) associated with a comparator (not shown) which compares the value issued by the flip-flop counter with a threshold stored in register 5. When the threshold is reached, timer 2 positions its output signal S to a high or low state according to the state of a control bit contained in register 4. Timer 2 is reset by a signal ResetC from CPU 1.
FIG. 2 shows, in the form of timing diagrams, an example of a signal S comprising a sequence of pulse trains obtained by means of a generator such as shown in FIG. 1. Sequence S here is comprised of three trains T1, T2, and T3 respectively including three, two and four pulses I. The rising and falling edges of each pulse I are generated by the circuit such as shown in FIG. 1, that is, for each state switching of signal S, CPU 1 must load into registers 4 and 5, respectively, a control bit indicating the high or low state which is to be adopted by signal S at the end of the previous state and a timing threshold determining the time position of the following edge. In the example shown, all pulses I have the same width. In the application to infrared remote controls, the pulse frequency generally is constant for a particular train sequence. However, the width and frequency of the pulses may be adjustable. Further, the pulse width generally corresponds to a shape factor (pulse width for one period) ranging between 30 and 50% of the pulse period for the entire sequence.
Signal CLK0 has not been shown in FIG. 2. It should be noted that the frequency of signal CLK0 is clearly higher than the frequency of the pulses I of a train. A higher frequency of CLK0 signal is needed because, in order to program registers 4 and 5, CPU 1 has to perform two programming cycles between each pulse edge of signal S while each programming cycle requires several clock cycles. Thus, the need for programming registers 4 and 5 prior to each desired edge of signal S, takes CPU 1 a considerable length of time. As a result, CPU 1 is not available to perform other tasks. This is a disadvantage of conventional generators such as the one shown in FIG. 1.
U.S. Pat. No. 5,319,487 discloses a pulse train generator in which an envelope signal is modulated by a fixed frequency carrier. That carrier is generated independently from the envelope signal which is obtained by an encoder controlled by a keyboard. A drawback of that generator is that the envelope and carrier signals are not synchronized with each other. Therefore some head and tail carrier pulses may be shortened during modulation, causing loss of information. Another drawback is that the pulse train generator is not versatile and cannot be tuned to different carrier frequencies.